Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays
نویسندگان
چکیده
As the capacities of eld-programmable gate arrays (FPGAs) grow, it becomes desirable to create FPGAs with embedded memory arrays. This paper examines the exibility of the interconnect structure that joins memory and logic. For architectures with only a few memory arrays, we nd that both the routability and the delay of circuits are insensitive to the memory/logic interconnect exibility, which implies that this interconnection can be made very in exible. This is in contrast to the logic connection block exibility, which has been shown to require high exibility [1]. For architectures with more arrays, the memory/logic interconnect exibility requirements increase and approach those of logic interconnect.
منابع مشابه
The memory/logic interface in FPGAs with large embedded memory arrays
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